HD64F3028F25 Datasheet, PDF (641/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

3. All blocks are unerasable and block-by-block specification is not possible.
4. See section 4.2.2, Reset Sequence, and section 18.11, Flash Memory Programming
and Erasing Precautions. The H8/3028F-ZTAT requires a minimum of 20 system clock
cycles for a reset during operation.
18.7.2 Software Protection
Software protection can be implemented by setting the erase block register 1 (EBR1), erase block
register 2 (EBR2), and the RAMS bit in the RAM control register (RAMCR). With software
protection, setting the P or E bit in the flash memory control register 1 (FLMCR1) does not cause
a transition to program mode or erase mode. (See table 18.9.)
Table 18.9 Software Protection
Functions
Item
Description
Program Erase
Verify
Block
protection
• Erase protection can be set for individual —
blocks by settings in erase block register 1
(EBR1) and erase block register 2
(EBR2)^*2. However, programming
protection is disabled.
Not
possible
Possible
• Setting EBR1 and EBR2 to H'00 places all
blocks in the erase-protected state.
Emulation
protection
• Setting the RAMS bit 1 in RAMCR places
all blocks in the program/erase-protected
state.
Not
Not
Possible
possible^*1 possible^*3
Notes: 1. The RAM area overlapping flash memory can be written to.
2. When not erasing, set EBR1 and EBR2 to H'00.
3. All blocks are unerasable and block-by-block specification is not possible.
18.7.3 Error Protection
In error protection, an error is detected when MCU runaway occurs during flash memory
programming/erasing*¹, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in
the flash memory status register (FLMSR2) and the error protection state is entered. FLMCR1,
FLMCR2, EBR1, and EBR2 settings*³ are retained, but program mode or erase mode is aborted at
the point at which the error occurred. Program mode or erase mode cannot be re-entered by re-
Rev. 2.00, 09/03, page 609 of 890