HD64F3028F25 Datasheet, PDF (830/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

TCR0—Timer Control Register
H'FFF68
16-bit timer channel 0
Bit
7
6
5
4
3
2
1
0
— _{CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0}
Initial value
1
Read/Write —
0
0
0
0
0
0
0
R/W
R/W R/W R/W
R/W
R/W R/W
Timer prescaler 2 to 0
Bit 2
Bit 1
Bit 0
TPSC2
0
TPSC1
0
1
TPSC0
0
1
0
1
0
0
1
1
0
1
1
TCNT Clock Source
Internal clock : φ
Internal clock : φ/2
Internal clock : φ/4
Internal clock : φ/8
External clock A : TCLKA input
External clock B : TCLKB input
External clock C : TCLKC input
External clock D : TCLKD input
(Initial value)
Clock edge 1 and 0
Bit 4 Bit 3
CKEG1 CKEG0
0
0
0
1
1
—
Counted Edges of External Clock
Rising edges counted
Falling edges counted
Both edges counted
(Initial value)
Counter clear 1 and 0
Bit 6
CCLR1
Bit 5
CCLR0
TCNT clear Sources
0
0
TCNT is not cleared
(Initial value)
1
TCNT is cleared by GRA compare match or input capture
1
0
TCNT is cleared by GRB compare match or input capture
Synchronous clear : TCNT is cleared in synchronization with other
1
synchronized timers
Rev. 2.00, 09/03, page 798 of 890