HD64F3028F25 Datasheet, PDF (481/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 13 Serial Communication Interface
13.1 Overview
The H8/3028 Group has a serial communication interface (SCI) with three independent channels.
All three channels have identical functions. The SCI can communicate in both asynchronous and
synchronous mode. It also has a multiprocessor communication function for serial communication
among two or more processors.
When the SCI is not used, it can be halted to conserve power. Each SCI channel can be halted
independently. For details, see section 20.6, Module Standby Function.
The SCI also has a smart card interface function conforming to the ISO/IEC 7816-3 (Identification
Card) standard. This function supports serial communication with a smart card. Switching
between the normal serial communication interface and the smart card interface is carried out by
means of a register setting.
13.1.1 Features
SCI features are listed below.
• Selection of synchronous or asynchronous mode for serial communication
Asynchronous mode
Serial data communication is synchronized one channel at a time. The SCI can communicate
with a universal asynchronous receiver/transmitter (UART), asynchronous communication
interface adapter (ACIA), or other chip that employs standard asynchronous communication.
It can also communicate with two or more other processors using the multiprocessor
communication function. There are twelve selectable serial data transfer formats.
 Data length:
7 or 8 bits
 Stop bit length:
1 or 2 bits
 Parity:
even/odd/none
 Multiprocessor bit:
1 or 0
 Receive error detection: parity, overrun, and framing errors
 Break detection:
by reading the RxD level directly when a framing error occurs
Synchronous mode
Serial data communication is synchronized with a clock signal. The SCI can communicate
with other chips having a synchronous communication function.
There is a single serial data communication format.
 Data length:
8 bits
 Receive error detection: overrun errors
Rev. 2.00, 09/03, page 449 of 890