HD64F3028F25 Datasheet, PDF (391/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Timing of Setting of Overflow Flag (OVF): OVF is set to 1 when 16TCNT overflows from
H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 9.35 shows the timing.
φ
16TCNT
Overflow
signal
OVF
OVI
Figure 9.35 Timing of Setting of OVF
9.5.2 Timing of Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 9.36 shows the timing.
TISR write cycle
T₁
T₂
T₃
φ
Address
TISR address
IMF, OVF
Figure 9.36 Timing of Clearing of Status Flags
Rev. 2.00, 09/03, page 359 of 890