HD64F3028F25 Datasheet, PDF (354/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Bit 5—Input Capture/Compare Match Interrupt Enable A1 (IMIEA1): Enables or disables
the interrupt requested by the IMFA1 flag when IMFA1 is set to 1.
Bit 5
IMIEA1
0
1
Description
IMIA1 interrupt requested by IMFA1 flag is disabled
IMIA1 interrupt requested by IMFA1 flag is enabled
(Initial value)
Bit 4—Input Capture/Compare Match Interrupt Enable A0 (IMIEA0): Enables or disables
the interrupt requested by the IMFA0 flag when IMFA0 is set to 1.
Bit 4
IMIEA0
0
1
Description
IMIA0 interrupt requested by IMFA0 flag is disabled
IMIA0 interrupt requested by IMFA0 flag is enabled
(Initial value)
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—Input Capture/Compare Match Flag A2 (IMFA2): This status flag indicates GRA2
compare match or input capture events.
Bit 2
IMFA2
0
1
Description
[Clearing conditions]
(Initial value)
• Read IMFA2 flag when IMFA2 =1, then write 0 in IMFA2 flag
• DMAC is activated by an IMIA2 interrupt
[Setting conditions]
• 16TCNT2 = GRA2 when GRA2 functions as an output compare register
• 16TCNT2 value is transferred to GRA2 by an input capture signal when GRA2
functions as an input capture register
Rev. 2.00, 09/03, page 322 of 890