HD64F3028F25 Datasheet, PDF (907/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Hardware
Pin
Standby Software Standby
Name Mode Reset Mode
Mode
Bus-Released
Mode
Program Execution
Mode
PB3 1 to 5 T
T
• RAS4 output^*12
(SSOE=0)
T
(SSOE=1)
H
• CS output^*13
(SSOE=0)
T
(SSOE=1)
H
• Otherwise^*14
Keep
• RAS4 output^*12
T
• CS output^*13
T
• Otherwise^*14
Keep
• RAS4 output
RAS4
• CS output
CS4
• Otherwise
I/O port
6, 7 T
T
PB5 to 1 to 5 T
T
PB4
Keep
• CAS output^*15
(SSOE=0)
T
(SSOE=1)
H
• Otherwise^*16
Keep
—
• CAS output^*15
T
• Otherwise^*16
Keep
I/O port
• CAS output
UCAS, LCAS
• Otherwise
I/O port
6, 7 T
T
Keep
—
I/O port
PB7 to 1 to 7 T
T
PB4
RESO^*1 —
T^*1
T
Keep
T
Keep
T^*1
I/O port
T
Legend
H: High
L:
Low
T: High-impedance state
Keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register
Notes: 1. When bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control register A) are all
cleared to 0.
2. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
set to 1.
3. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is 010, 100, or 101.
4. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 010, 100, 101, or 000.
5. When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is
cleared to 0.
6. When bit A23E, A22E, or A21E, respectively, in BRCR (bus release control register) is
set to 1.
7. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is set to
1.
Rev. 2.00, 09/03, page 875 of 890