HD64F3028F25 Datasheet, PDF (865/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

ADDRC H/L—A/D Data Register C H/L
H'FFFE4,
A/D
H'FFFE5
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R R R R R R R R R
ADDRCH
ADDRCL
A/D conversion data
10-bit data giving an A/D conversion result
ADDRD H/L—A/D Data Register D H/L
H'FFFE6,
A/D
H'FFFE7
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Read/Write R R R R R R R R R R R R R R R R
ADDRDH
ADDRDL
ADCR—A/D Control Register
Bit
7
6
TRGE
—
Initial value
0
1
Read/Write R/W
—
A/D conversion data
10-bit data giving an A/D conversion result
H'FFFE9
5
4
3
2
1
—
—
—
—
—
1
1
1
1
1
—
—
—
—
—
A/D
0
—
0
R/W
Trigger Enable
A/D conversion start by external trigger or 8-bit timer
0 _{compare match is disabled}
1
A/D conversion is started by falling edge of external
trigger signal (ADTRG) or 8-bit timer compare match
Rev. 2.00, 09/03, page 833 of 890