HD64F3028F25 Datasheet, PDF (470/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the WDT.
Overflow
Interrupt signal
Interrupt
(interval timer) ^control
TCNT
TCSR
Reset
(internal, external)
RSTCSR
Reset control
Clock
Clock
selector
Read/
write
control
Internal
data bus
Internal clock sources
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
RESO*
Legend
TCNT: Timer counter
TCSR: Timer control/status register
RSTCSR: Reset control/status register
Note: * Open-drain output pin
Figure 12.1 WDT Block Diagram
12.1.3 Pin Arrangement
The pins*¹ used by the watchdog timer are listed in table 12.1.
Table 12.1
Name
Reset output
Abbreviation
RESO
I/O
Output^*2
Notes: 1. Not available on flash memory version.
2. Open drain output pin.
Function
Outputs watchdog timer reset signal to
external device
Rev. 2.00, 09/03, page 438 of 890