HD64F3028F25 Datasheet, PDF (475/925 Pages) Renesas Technology Corp – Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Bit 6—Reset Output Enable (RSTOE): Enables or disables output of the reset signal from the
RESO pin when TCNT overflow generates a reset signal during watchdog timer operation. Note
that the flash memory version is not equipped with a RESO pin.
Bit 6
RSTOE
0
1
Description
External output of reset signal disabled.
External output of reset signal enabled.
Bits 5 to 0—Reserved: These bits are reserved. They cannot be written to and are always read
as 1.
12.2.4 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte instructions. Figure 12.2 shows the format of data written to
TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be
contained in the lower byte of the written word. The upper byte must contain H'5A (password for
TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT
or TCSR.
TCNT write
15
Address H'FFF8C*
H'5A
87
0
Write data
TCSR write
15
Address H'FFF8C*
H'A5
87
0
Write data
Note: * Lower 20 bits of the address in advanced mode.
Figure 12.2 Format of Data Written to TCNT and TCSR
Rev. 2.00, 09/03, page 443 of 890