HD64F38024HV Datasheet, PDF (92/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 2 CPU
To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PDR3.
[A: Prior to executing BSET]
MOV. B #80, R0L
MOV. B R0L, @RAM0
MOV. B R0L, @PDR3
The PDR3 value (H'80) is written to a work area in memory
(RAM0) as well as to PDR3
P37
P36
P35
P34
P33
P32
P31
P30
Input/output Input Input Output Output Output Output Output Output
Pin state Low level High level Low level Low level Low level Low level Low level Low level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
0
RAM0
1
0
0
0
0
0
0
0
[B: BSET instruction executed]
BSET #0 , @RAM0
The BSET instruction is executed designating the PDR3
work area (RAM0).
[C: After executing BSET]
MOV. B @RAM0, R0L
MOV. B R0L, @PDR3
The work area (RAM0) value is written to PDR3.
P37
P36
P35
P34
P33
P32
P31
P30
Input/output Input Input Output Output Output Output Output Output
Pin state Low level High level Low level Low level Low level Low level Low level High level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
1
RAM0
1
0
0
0
0
0
0
1
Rev. 8.00 Mar. 09, 2010 Page 70 of 658
REJ09B0042-0800