HD64F38024HV Datasheet, PDF (573/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Appendix B Internal I/O Registers
B.2 Functions
Register name
Register acronym
Bit numbers
TCRF⎯Timer Control Register F
Address to which the register is mapped.
When displayed with two-digit number,
this indicates the lower address,
and the upper address is HFF.
H'B6
Timer F
Name of on-chip
supporting module
Initial bit values
Dashes (⎯) indicate
undefined bits.
Possible types of access
R Read only
W Write only
R/W Read and write
⎯ See relevant register
description
Bit
7
6
5
4
3
2
1
0
TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0
Initial value 0
0
0
0
0
0
0
0
R/W
W
W
W
W
W
W
W
W
Clock select L
Counts on external event (TMIF) rising/
0 * * _{falling edge}
1 0 0 Internal clock: φ/32
1 0 1 Internal clock: φ/16
1 1 0 Internal clock: φ/4
1 1 1 Internal clock: φw/4
Toggle output level L
0 Set to low level
1 Set to high level
Names of the bits.
Dashes (⎯) indicate
reserved bits.
Full name of bit
Descriptions of bit
settings
Clock select H
0 * * 16-bit mode, counts on TCFL overflow signal
1 0 0 Internal clock: φ/32
1 0 1 Internal clock: φ/16
1 1 0 Internal clock: φ/4
1 1 1 Internal clock: φw/4
Toggle output level H
0 Set to low level
1 Set to high level
* Don't care
Rev. 8.00 Mar. 09, 2010 Page 551 of 658
REJ09B0042-0800