HD64F38024HV Datasheet, PDF (77/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 2 CPU
2.6 Basic Operational Timing
CPU operation is synchronized by a system clock (φ) or a subclock (φ_SUB). For details on these
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φ_SUB to
the next rising edge is called one state. A bus cycle consists of two states or three states. The
cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing
access in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
φ or φ_SUB
Bus cycle
T₁ state
T₂ state
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.11 On-Chip Memory Access Cycle
Rev. 8.00 Mar. 09, 2010 Page 55 of 658
REJ09B0042-0800