HD64F38024HV Datasheet, PDF (91/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 2 CPU
Example 2: BSET instruction executed designating port 3
P3₇ and P3₆ are designated as input pins, with a low-level signal input at P3₇ and a high-level
signal at P3₆. The remaining pins, P3₅ to P3₁, are output pins and output low-level signals. In this
example, the BSET instruction is used to change pin P3₀ to high-level output.
[A: Prior to executing BSET]
P37
P36
P35
P34
P33
P32
P31
P30
Input/output Input Input Output Output Output Output Output Output
Pin state Low level High level Low level Low level Low level Low level Low level Low level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
0
[B: BSET instruction executed]
BSET #0 , @PDR3
The BSET instruction is executed designating port 3.
[C: After executing BSET]
P37
P36
P35
P34
P33
P32
P31
P30
Input/output Input Input Output Output Output Output Output Output
Pin state Low level High level Low level Low level Low level Low level Low level High level
PCR3
0
0
1
1
1
1
1
1
PDR3
0
1
0
0
0
0
0
1
[D: Explanation of how BSET operates]
When the BSET instruction is executed, first the CPU reads port 3.
Since P3₇ and P3₆ are input pins, the CPU reads the pin states (low-level and high-level input).
P3₅ to P3₀ are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value
of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU
writes this value (H'41) to PDR3, completing execution of BSET.
As a result of this operation, bit 0 in PDR3 becomes 1, and P3₀ outputs a high-level signal.
However, bits 7 and 6 of PDR3 end up with different values.
Rev. 8.00 Mar. 09, 2010 Page 69 of 658
REJ09B0042-0800