HD64F38024HV Datasheet, PDF (591/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

RDR—Receive Data Register
Appendix B Internal I/O Registers
H'AD
SCI3
Bit
Initial value
Read/Write
7
RDR7
0
R
6
RDR6
0
R
5
RDR5
0
R
4
RDR4
0
R
3
RDR3
0
R
2
RDR2
0
R
1
RDR1
0
R
0
RDR0
0
R
Serial receiving data are stored
TMA—Timer Mode Register A
H'B0
Timer A
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
TMA3 TMA2 TMA1 TMA0
Initial value
⎯
⎯
⎯
1
0
0
0
0
Read/Write
W
W
W
⎯
R/W R/W
R/W
R/W
Internal Clock Select
Prescaler and Divider Ratio
TMA3 TMA2 TMA1 TMA0 or Overflow Period
0
0
0
0 PSS
φ/8192
1 PSS
φ/4096
1
0 PSS
φ/2048
1 PSS
φ/512
1
0
0 PSS
φ/256
1 PSS
φ/128
1
0 PSS
φ/32
1 PSS
φ/8
1
0
0
0 PSW
1s
1 PSW
0.5 s
1
0 PSW
0.25 s
1 PSW
0.03125 s
1
0
0 PSW and TCA are reset
1
1
0
1
Function
Interval
timer
Clock time
base
(when
using
32.768 kHz)
Rev. 8.00 Mar. 09, 2010 Page 569 of 658
REJ09B0042-0800