HD64F38024HV Datasheet, PDF (564/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Appendix A CPU Instruction Set
Table A.4 Number of Cycles in Each Instruction
Instruction
ADD
ADDS
ADDX
AND
ANDC
BAND
Bcc
BCLR
BIAND
Mnemonic
ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W Rs, Rd
ADDS.W #1, Rd
ADDS.W #2, Rd
ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
AND.B #xx:8, Rd
AND.B Rs, Rd
ANDC #xx:8, CCR
BAND #xx:3, Rd
BAND #xx:3, @Rd
BAND #xx:3, @aa:8
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
BCLR #xx:3, Rd
BCLR #xx:3, @Rd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @Rd
BCLR Rn, @aa:8
BIAND #xx:3, Rd
BIAND #xx:3, @Rd
BIAND #xx:3, @aa:8
Instruction Branch
Stack
Fetch
Addr. Read Operation
I
J
K
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
1
2
2
1
2
2
Byte Data
Access
L
1
1
2
2
2
2
1
1
Word Data Internal
Access
Operation N
M
Rev. 8.00 Mar. 09, 2010 Page 542 of 658
REJ09B0042-0800