HD64F38024HV Datasheet, PDF (67/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 2 CPU
Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions.
15
op
87
rm
15
87
op
15
op
87
rm
0
rn
ADD, SUB, CMP,
ADDX, SUBX (Rm)
0
rn
ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT
0
rn
MULXU, DIVXU
15
op
87
rn
IMM
0
ADD, ADDX, SUBX,
CMP (#XX:8)
15
op
87
rm
0
rn
AND, OR, XOR (Rm)
15
op
87
rn
IMM
0
AND, OR, XOR (#xx:8)
15
87
op
0
rn
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
[Legend]
op: Operation field
rm, rn: Register field
IMM: Immediate data
Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes
Rev. 8.00 Mar. 09, 2010 Page 45 of 658
REJ09B0042-0800