HD64F38024HV Datasheet, PDF (223/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 8 I/O Ports
This section only deals with the bits related to timer G and the watchdog timer. For the functions
of the bits, see the descriptions of port 3 (POF1) and port 4 (IRQ0).
Bit 2—Watchdog Timer Source Clock (WDCKS)
This bit selects the watchdog timer source clock. Note that stabilization times for the H8/38024,
H8/38024S, and H8/38024R Group and for the H8/38124 Group are different.
• H8/38024, H8/38024S, H8/38024R Group
Bit 2
WDCKS
Description
0
Selects φ/8192
1
Selects φW/32
(initial value)
• H8/38124 Group
Bit 2
WDCKS
Description
0
Selects clock based on timer mode register W (TMW) setting^*
1
Selects φW/32
Note: * See section 9.6, Watchdog Timer, for details.
(initial value)
Bit 1—TMIG Noise Canceller Select (NCS)
This bit selects controls the noise cancellation circuit of the input capture input signal (TMIG).
Bit 1
NCS
0
1
Description
No noise cancellation circuit
Noise cancellation circuit
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 201 of 658
REJ09B0042-0800