HD64F38024HV Datasheet, PDF (374/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 10 Serial Communication Interface
Table 10.4 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
0
φw/2^*1/φw^*2
0
1
2
φ/16
1
0
3
φ/64
1
1
Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode
2. φ w clock in subactive mode and subsleep mode
In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only.
Table 10.5 shows the maximum bit rate for each frequency. The values shown are for active
(high-speed) mode.
Table 10.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
OSC (MHz)
φ (MHz)
Maximum Bit Rate
(bit/s)
n
0.0384^*
0.0192
600
0
2
1
31250
0
2.4576
1.2288
38400
0
4
2
62500
0
10
5
156250
0
16
8
250000
0
20
10
312500
0
Note: * When SMR is set up to CKS1 = 0, CKS0 = 1.
Setting
N
0
0
0
0
0
0
0
Rev. 8.00 Mar. 09, 2010 Page 352 of 658
REJ09B0042-0800