HD64F38024HV Datasheet, PDF (306/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 9 Timers
Block Diagram
Figure 9.8 shows a block diagram of timer G.
φ
PSS
φ_W/4
TMG
ICRGF
Level
detector
TMIG
Noise
canceler
Edge
detector
TCG
NCS
ICRGR
IRRTG
[Legend]
TMG: Timer mode register G
TCG: Timer counter G
ICRGF: Input capture register GF
ICRGR: Input capture register GR
IRRTG: Timer G interrupt request flag
NCS: Noise canceler select
PSS: Prescaler S
Figure 9.8 Block Diagram of Timer G
Pin Configuration
Table 9.10 shows the timer G pin configuration.
Table 9.10 Pin Configuration
Name
Input capture input
Abbr.
TMIG
I/O
Input
Function
Input capture input pin
Rev. 8.00 Mar. 09, 2010 Page 284 of 658
REJ09B0042-0800