HD64F38024HV Datasheet, PDF (556/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Appendix A CPU Instruction Set
Addressing Mode/
Instruction Length (bytes)
Mnemonic
MULXU.B Rs, Rd
DIVXU.B Rs, Rd
AND.B #xx:8, Rd
AND.B Rs, Rd
OR.B #xx:8, Rd
OR.B Rs, Rd
XOR.B #xx:8, Rd
XOR.B Rs, Rd
NOT.B Rd
SHAL.B Rd
SHAR.B Rd
SHLL.B Rd
SHLR.B Rd
ROTXL.B Rd
ROTXR.B Rd
Operation
B Rd8 × Rs8 → Rd16
2
B Rd16÷Rs8 → Rd16
2
(RdH: remainder,
RdL: quotient)
B Rd8∧#xx:8 → Rd8
2
B Rd8∧Rs8 → Rd8
2
B Rd8∨#xx:8 → Rd8
2
B Rd8∨Rs8 → Rd8
2
B Rd8⊕#xx:8 → Rd8
2
B Rd8⊕Rs8 → Rd8
2
B Rd → Rd
2
BC
0
2
b₇
b₀
B
C
2
b₇
b₀
BC
0
2
b₇
b₀
B0
C
2
b₇
b₀
BC
2
b₇
b₀
B
2
b₇
b₀ C
Condition Code
I HNZVC
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 14
⎯ ⎯ (5) (6) ⎯ ⎯ 14
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
⎯⎯
0⎯2
0⎯2
0⎯2
0⎯2
0⎯2
0⎯2
0⎯2
2
⎯⎯
02
⎯⎯
02
⎯⎯ 0 0 2
⎯⎯
02
⎯⎯
02
Rev. 8.00 Mar. 09, 2010 Page 534 of 658
REJ09B0042-0800