HD64F38024HV Datasheet, PDF (350/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 9 Timers
Figure 9.22 and table 9.20 show examples of event counter PWM operation.
toff = T × (Ndr +1)
ton
tcm = T × (Ncm +1)
T_on :
T_off :
T_cm :
T:
Clock input enabled time
Clock input disabled time
One conversion period
ECPWM input clock cycle
N_dr : Value of ECPWDRH and ECPWDRL
Fixed low when Ndr = H'FFFF
N_cm : Value of ECPWCRH and ECPWCRL
Figure 9.22 Event Counter Operation Waveform
Note: N_dr and N_cm above must be set so that N_dr < N_cm. If the settings do not satisfy this
condition, do not set ECPWME in AEGSR to 1.
Table 9.20 Examples of Event Counter PWM Operation
Conditions: f_osc = 4 MHz, f_φ = 2 MHz, high-speed active mode, ECPWCR value (N_cm) = H'7A11,
ECPWDR value (N_dr) = H'16E3
Clock Source Clock Source ECPWCR ECPWDR
Selection
Cycle (T)^*
Value (Ncm) Value (Ndr)
φ/2
1 µs
H'7A11
H'16E3
φ/4
2 µs
D'31249 D'5859
φ/8
4 µs
φ/16
8 µs
φ/32
16 µs
φ/64
32 µs
Note: * toff minimum width
toff = T •
(Ndr + 1)
5.86 ms
11.72 ms
23.44 ms
46.88 ms
93.76 ms
187.52 ms
tcm = T •
(Ncm + 1)
31.25 ms
62.5 ms
125.0 ms
250.0 ms
500.0 ms
1000.0 ms
ton = tcm – toff
25.39 ms
50.78 ms
101.56 ms
203.12 ms
406.24 ms
812.48 ms
Rev. 8.00 Mar. 09, 2010 Page 328 of 658
REJ09B0042-0800