HD64F38024HV Datasheet, PDF (166/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 5 Power-Down Modes
Register Name Bit Name
Operation
CKSTPR2
LDCKSTP
1
LCD module standby mode is cleared
0
LCD is set to module standby mode
PW1CKSTP 1
PWM1 module standby mode is cleared
0
PWM1 is set to module standby mode
WDCKSTP
1
Watchdog timer module standby mode is cleared
0
Watchdog timer is set to module standby mode
AECKSTP
1
Asynchronous event counter module standby mode
is cleared
0
Asynchronous event counter is set to module standby
mode
PW2CKSTP 1
PWM2 module standby mode is cleared
0
PWM2 is set to module standby mode
LVDCKSTP* 1
LVD module standby mode is cleared
0
LVD is set to module standby mode
Notes: For details of module operation, see the sections on the individual modules.
* LVDCKSTP is implemented on the H8/38124 group only.
5.10 Usage Note
5.10.1 Contention Between Module Standby and Interrupts
If, due to timing with which a peripheral module issues interrupt requests, the module in question
is set to module standby mode before an interrupt is processed, the module will stop with the
interrupt request still pending. In this situation, interrupt processing will be repeated indefinitely
unless interrupts are prohibited.
It is therefore necessary to ensure that no interrupts are generated when a module is set to module
standby mode. The surest way to do this is to specify the module standby mode setting only when
interrupts are prohibited (interrupts prohibited using the interrupt enable register or interrupts
masked using bit CCR-1).
Rev. 8.00 Mar. 09, 2010 Page 144 of 658
REJ09B0042-0800