HD64F38024HV Datasheet, PDF (633/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

CKSTPR2—Clock Stop Register 2
Appendix B Internal I/O Registers
H'FB
System Control
Bit
7
6
LVDCKSTP* ⎯
Initial value
1
1
Read/Write
R/W
⎯
5
4
3
2
1
0
⎯ PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP
1
1
1
1
1
1
⎯
R/W R/W R/W R/W R/W
LCD Module Standby Mode Control
0 LCD is set to module standby mode
1 LCD module standby mode is cleared
PWM1 Module Standby Mode Control
0 PWM1 is set to module standby mode
1 PWM1 module standby mode is cleared
WDT Module Standby Mode Control
0 WDT is set to module standby mode
1 WDT module standby mode is cleared
Asynchronous Event Counter Module Standby Mode Control
0 Asynchronous event counter is set to module standby mode
1 Asynchronous event counter module standby mode is cleared
PWM2 Module Standby Mode Control
0 PWM2 is set to module standby mode
1 PWM2 module standby mode is cleared
LVD Module Standby Mode Control
0 LVD is set to module standby mode
1 LVD module standby mode is cleared
Note: * Control using the LVDCKST bit is implemented on the H8/38124 Group only.
Rev. 8.00 Mar. 09, 2010 Page 611 of 658
REJ09B0042-0800