HD64F38024HV Datasheet, PDF (187/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 6 ROM
Bit 7—Power-down Disable (PDWND)
This bit selects the power-down mode of the flash memory when a transition to the subactive
mode is made.
Bit 7
PDWND
0
1
Description
When this bit is 0 and a transition is made to the subactive mode, the flash memory
enters the power-down mode.
(initial value)
When this bit is 1, the flash memory remains in the normal mode even after a
transition is made to the subactive mode.
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
6.6.5 Flash Memory Enable Register (FENR)
Bit
7
6
5
4
3
2
1
0
FLSHE —
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write R/W
—
—
—
—
—
—
—
FENR controls CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR, and
FLPWCR.
Bit 7—Flash Memory Control Register Enable (FLSHE)
This bit controls access to the flash memory control registers.
Bit 7
FLSHE
0
1
Description
Flash memory control registers cannot be accessed
Flash memory control registers can be accessed
(initial value)
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
Rev. 8.00 Mar. 09, 2010 Page 165 of 658
REJ09B0042-0800