HD64F38024HV Datasheet, PDF (18/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

10.2.5 Serial Mode Register (SMR)................................................................................. 339
10.2.6 Serial Control Register 3 (SCR3).......................................................................... 342
10.2.7 Serial Status Register (SSR) ................................................................................. 346
10.2.8 Bit Rate Register (BRR) ....................................................................................... 350
10.2.9 Clock stop register 1 (CKSTPR1)......................................................................... 356
10.2.10 Serial Port Control Register (SPCR)..................................................................... 356
10.3 Operation............................................................................................................................ 358
10.3.1 Overview............................................................................................................... 358
10.3.2 Operation in Asynchronous Mode ........................................................................ 362
10.3.3 Operation in Synchronous Mode .......................................................................... 371
10.4 Interrupts ............................................................................................................................ 379
10.5 Application Notes .............................................................................................................. 380
Section 11 10-Bit PWM ....................................................................................385
11.1 Overview............................................................................................................................ 385
11.1.1 Features................................................................................................................. 385
11.1.2 Block Diagram ...................................................................................................... 386
11.1.3 Pin Configuration.................................................................................................. 387
11.1.4 Register Configuration.......................................................................................... 388
11.2 Register Descriptions ......................................................................................................... 388
11.2.1 PWM Control Register (PWCRm)........................................................................ 388
11.2.2 PWM Data Registers U and L (PWDRUm, PWDRLm)....................................... 390
11.2.3 Clock Stop Register 2 (CKSTPR2)....................................................................... 391
11.3 Operation............................................................................................................................ 392
11.3.1 Operation .............................................................................................................. 392
11.3.2 PWM Operation Modes ........................................................................................ 393
Section 12 A/D Converter .................................................................................395
12.1 Overview............................................................................................................................ 395
12.1.1 Features................................................................................................................. 395
12.1.2 Block Diagram ...................................................................................................... 396
12.1.3 Pin Configuration.................................................................................................. 397
12.1.4 Register Configuration.......................................................................................... 397
12.2 Register Descriptions ......................................................................................................... 398
12.2.1 A/D Result Registers (ADRRH, ADRRL)............................................................ 398
12.2.2 A/D Mode Register (AMR) .................................................................................. 398
12.2.3 A/D Start Register (ADSR)................................................................................... 400
12.2.4 Clock Stop Register 1 (CKSTPR1)....................................................................... 401
12.3 Operation............................................................................................................................ 402
12.3.1 A/D Conversion Operation ................................................................................... 402
Rev. 8.00 Mar. 09, 2010 Page xvi of xx
REJ09B0042-0800