HD64F38024HV Datasheet, PDF (390/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 10 Serial Communication Interface
• Receiving
Figure 10.8 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Start
Read bits OER,
PER, FER in SSR ^[1]
OER + PER
+ FER = 1?
No
Read bit RDRF
in SSR
Yes
[2]
RDRF = 1?
Yes
Read receive
data in RDR
No
Receive error
processing
[3]
Continue data
Yes
reception?
No
(A)
Clear bit RE to
0 in SCR3
[1] Read bits OER, PER, and FER in the
serial status register (SSR) to determine
if there is an error. If a receive error has
occurred, execute receive error
processing.
[2] Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data
in RDR. When the RDR data is read,
bit RDRF is cleared to 0 automatically.
[3] When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the stop bit of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
[4]
End
Figure 10.8 Example of Data Reception Flowchart (Asynchronous Mode)
Rev. 8.00 Mar. 09, 2010 Page 368 of 658
REJ09B0042-0800