HD64F38024HV Datasheet, PDF (103/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Interrupt Enable Register 1 (IENR1)
Section 3 Exception Handling
Bit
Initial value
Read/Write
7
IENTA
0
R/W
6
5
4
3
2
1
0
⎯ IENWP IEN4 IEN3 IENEC2 IEN1 IEN0
⎯
0
0
0
0
0
0
W
R/W R/W R/W R/W R/W R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Timer A Interrupt Enable (IENTA)
Bit 7 enables or disables timer A overflow interrupt requests.
Bit 7
IENTA
0
1
Description
Disables timer A interrupt requests
Enables timer A interrupt requests
(initial value)
Bit 6—Reserved
Bit 6 is reserved: it can only be written with 0.
Bit 5—Wakeup Interrupt Enable (IENWP)
Bit 5 enables or disables WKP₇ to WKP₀ interrupt requests.
Bit 5
IENWP
0
1
Description
Disables WKP7 to WKP0 interrupt requests
Enables WKP7 to WKP0 interrupt requests
(initial value)
Bits 4 and 3—IRQ₄ and IRQ₃ Interrupt Enable (IEN4 and IEN3)
Bits 4 and 3 enable or disable IRQ₄ and IRQ₃ interrupt requests.
Bit n
IENn
0
1
Description
Disables interrupt requests from pin IRQn
Enables interrupt requests from pin IRQn
(initial value)
(n = 4 or 3)
Rev. 8.00 Mar. 09, 2010 Page 81 of 658
REJ09B0042-0800