HD64F38024HV Datasheet, PDF (343/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Event Counter Control/Status Register (ECCSR)
Section 9 Timers
Bit
7
6
5
4
3
OVH
OVL
⎯
CH2
CUEH
Initial Value
0
0
0
0
0
Read/Write
R/W^*
R/W^*
R/W
R/W
R/W
Note: ^* Bits 7 and 6 can only be written with 0, for flag clearing.
2
CUEL
0
R/W
1
CRCH
0
R/W
0
CRCL
0
R/W
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
Bit 7—Counter Overflow H (OVH)
Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when
ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by
reading it when set to 1, then writing 0.
When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as a
status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000.
Bit 7
OVH
0
1
Description
ECH has not overflowed
Clearing condition:
After reading OVH = 1, cleared by writing 0 to OVH
ECH has overflowed
Setting condition:
Set when ECH overflows from H’FF to H’00
(initial value)
Bit 6—Counter Overflow L (OVL)
Bit 6 is a status flag indicating that ECL has overflowed from H'FF to H'00. This flag is set when
ECL overflows. It is cleared by software but cannot be set by software. OVL is cleared by
reading it when set to 1, then writing 0.
Rev. 8.00 Mar. 09, 2010 Page 321 of 658
REJ09B0042-0800