HD64F38024HV Datasheet, PDF (584/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Appendix B Internal I/O Registers
ECCSR—Event Counter Control/Status Register
H'95
AEC
Bit
Initial value
Read/Write
7
OVH
0
R/W
6
OVL
0
R/W
5
⎯
0
R/W
4
CH2
0
R/W
3
CUEH
0
R/W
2
CUEL
0
R/W
1
CRCH
0
R/W
0
CRCL
0
R/W
Counter Reset Control L
0 ECL is reset
1 ECL reset is cleared
and count-up function
is enabled
Counter Reset Control H
0 ECH is reset
1 ECH reset is cleared and
count-up function is enabled
Count-up Enable L
0 ECL event clock input is disabled.
ECL value is held
1 ECL event clock input is enabled
Count-up Enable H
0 ECH event clock input is disabled.
ECH value is held
1 ECH event clock input is enabled
Channel Select
0 ECH and ECL are used together as a single-
channel 16-bit event counter
1 ECH and ECL are used as two independent
8-bit event counter channels
Counter Overflow L
0 ECL has not overflowed
1 ECL has overflowed
Counter Overflow H
0 ECH has not overflowed
1 ECH has overflowed
Rev. 8.00 Mar. 09, 2010 Page 562 of 658
REJ09B0042-0800