HD64F38024HV Datasheet, PDF (577/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Appendix B Internal I/O Registers
LVDCR—Low-Voltage Detection Control Register
H'86
Note: This register is implemented on the H8/38124 Group only.
LVDC
Bit
Initial value
Read/Write
7
LVDE
0^*
R/W
6
5
4
3
2
1
0
⎯ VINTDSEL VINTUSEL LVDSEL LVDRE LVDDE LVDUE
0
0
0
0^*
0^*
0
0
R/W
R/W
R/W
R/W R/W
R/W
R/W
Voltage Rise Interrupt Enable
0 Voltage rise interrupt requests disabled (initial value)
1 Voltage rise interrupt requests enabled
Voltage Drop Interrupt Enable
0 Voltage drop interrupt requests disabled (initial value)
1 Voltage drop interrupt requests enabled
LVDR Enable
0 LVDR resets disabled
1 LVDR resets enabled
(initial value)
LVDR Detection Level Select
0 Reset detection voltage 2.3 V (typ.)
1 Reset detection voltage 3.3 V (typ.)
(initial value)
Power Supply Rise (LVDU) Detection Level External Input Select
0 LVDU detection level generated by on-chip ladder resistor (initial value)
1 LVDU detection level input to extU pin
Power Supply Drop (LVDD) Detection Level External Input Select
0 LVDD detection level generated by on-chip ladder resistor (initial value)
1 LVDD detection level input to extD pin
LVD Enable
0 Low-voltage detection circuit not used (standby status) (initial value)
1 Low-voltage detection circuit use
Note: * These bits are not initialized by resets trigged by LVDR. They are initialized by
power-on resets and watchdog timer resets.
Rev. 8.00 Mar. 09, 2010 Page 555 of 658
REJ09B0042-0800