HD64F38024HV Datasheet, PDF (382/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 10 Serial Communication Interface
Interrupts and Continuous Transmission/Reception
SCI3 can carry out continuous reception using RXI and continuous transmission using TXI.
These interrupts are shown in table 10.10.
Table 10.10 Transmit/Receive Interrupts
Interrupt
RXI
TXI
TEI
Flags
RDRF
RIE
TDRE
TIE
TEND
TEIE
Interrupt Request Conditions
Notes
When serial reception is performed
The RXI interrupt routine reads the
normally and receive data is transferred receive data transferred to RDR and
from RSR to RDR, bit RDRF is set to 1, clears bit RDRF to 0. Continuous
and if bit RIE is set to 1 at this time, RXI reception can be performed by
is enabled and an interrupt is requested. repeating the above operations until
(See figure 10.2(a).)
reception of the next RSR data is
completed.
When TSR is found to be empty (on The TXI interrupt routine writes the
completion of the previous transmission) next transmit data to TDR and clears
and the transmit data placed in TDR is bit TDRE to 0. Continuous
transferred to TSR, bit TDRE is set to 1. transmission can be performed by
If bit TIE is set to 1 at this time, TXI is repeating the above operations until
enabled and an interrupt is requested. the data transferred to TSR has
(See figure 10.2(b).)
been transmitted.
When the last bit of the character in
TEI indicates that the next transmit
TSR is transmitted, if bit TDRE is set to data has not been written to TDR
1, bit TEND is set to 1. If bit TEIE is set when the last bit of the transmit
to 1 at this time, TEI is enabled and an character in TSR is sent.
interrupt is requested. (See figure
10.2(c).)
Rev. 8.00 Mar. 09, 2010 Page 360 of 658
REJ09B0042-0800