HD64F38024HV Datasheet, PDF (336/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 9 Timers
Block Diagram
Figure 9.19 shows a block diagram of the asynchronous event counter.
φ
PSS
ECCR
IRREC
ECCSR
φ/2
φ/4, φ/8
AEVH
Edge sensing
circuit
AEVL
IRQAEC
Edge sensing
circuit
Edge sensing
circuit
OVH
ECH
(8 bits) _CK
OVL
ECL
(8 bits) _CK
ECPWCRH
To CPU interrupt
(IRREC2)
ECPWCRL
φ/2, φ/4,
φ/8, φ/16,
φ/32, φ/64
AEGSR
PWM waveform generator
ECPWDRH
ECPWDRL
[Legend]
ECPWCRH:
ECPWDRH:
AEGSR:
ECCSR:
ECH:
ECL:
Event counter PWM compare register H
Event counter PWM data register H
Input pin edge select register
Event counter control/status register
Event counter H
Event counter L
ECPWCRL: Event counter PWM compare register L
ECPWDRL: Event counter PWM data register L
ECCR:
Event counter control register
Figure 9.19 Block Diagram of Asynchronous Event Counter
Rev. 8.00 Mar. 09, 2010 Page 314 of 658
REJ09B0042-0800