HD64F38024HV Datasheet, PDF (24/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 1 Overview
Table 1.1 Features
Item
CPU
Interrupts
Specification
High-speed H8/300L CPU
• General-register architecture
General registers: Sixteen 8-bit registers (can be used as eight 16-bit
registers)
• Operating speed
⎯ Max. operating speed: 8 MHz (5 MHz for HD64F38024 and H8/38024S
Group)
⎯ Add/subtract: 0.25 µs (operating at 8 MHz), 0.4 μs (operating at φ =
5 MHz)
⎯ Multiply/divide: 1.75 µs (operating at 8 MHz), 2.8 μs (operating at φ =
5 MHz)
⎯ Can run on 32.768 kHz or 38.4 kHz subclock (32.768 kHz only for
H8/38124 Group)
• Instruction set compatible with H8/300 CPU
⎯ Instruction length of 2 bytes or 4 bytes
⎯ Basic arithmetic operations between registers
⎯ MOV instruction for data transfer between memory and registers
• Typical instructions
⎯ Multiply (8 bits × 8 bits)
⎯ Divide (16 bits ÷ 8 bits)
⎯ Bit accumulator
⎯ Register-indirect designation of bit position
22 interrupt sources
• 13 external interrupt sources (IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0,
IRQAEC)
• 9 internal interrupt sources
Rev. 8.00 Mar. 09, 2010 Page 2 of 658
REJ09B0042-0800