HD64F38024HV Datasheet, PDF (630/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Appendix B Internal I/O Registers
TMW—Timer Mode Register W
H'F8
Note: This register is implemented on the H8/38124 Group only.
Watchdog Timer
Bit
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯ CKS3 CKS2 CKS1 CKS0
Initial value
1
1
1
1
1
1
1
1
Read/Write
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
Internal Clock Select
CDS3 CDS2 CDS1 CDS0
Clock source
1
0
0
0 φ/64
1
0
0
1 φ/128
1
0
1
0 φ/256
1
0
1
1 φ/512
1
1
0
0 φ/1024
1
1
0
1 φ/2048
1
1
1
0 φ/4096
1
1
1
1 φ/8192
0
*
*
* On-chip oscillator
Note: Valid when WDCKS bit in PMR2 register is cleared to 0.
Rev. 8.00 Mar. 09, 2010 Page 608 of 658
REJ09B0042-0800