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HD64F38024HV Datasheet, PDF (559/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series | |||
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Appendix A CPU Instruction Set
Addressing Mode/
Instruction Length (bytes)
Mnemonic
BIOR #xx:3, @aa:8
BXOR #xx:3, Rd
BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8
BIXOR #xx:3, Rd
BIXOR #xx:3, @Rd
BIXOR #xx:3, @aa:8
BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
JMP @Rn
JMP @aa:16
JMP @@aa:8
BSR d:8
Branching
Operation Condition
B Câ¨(#xx:3 of @aa:8) â C
B Câ(#xx:3 of Rd8) â C
B Câ(#xx:3 of @Rd16) â C
B Câ(#xx:3 of @aa:8) â C
B Câ(#xx:3 of Rd8) â C
B Câ(#xx:3 of @Rd16) â C
B Câ(#xx:3 of @aa:8) â C
⯠PC â PC+d:8
⯠PC â PC+2
⯠If
⯠condition
is true
⯠then
⯠PC â
PC+d:8
⯠else next;
â¯
Câ¨Z=0
Câ¨Z=1
C=0
C=1
Z=0
Z=1
â¯
V=0
â¯
V=1
â¯
N=0
â¯
N=1
â¯
NâV = 0
â¯
NâV = 1
â¯
Z ⨠(NâV) = 0
â¯
Z ⨠(NâV) = 1
⯠PC â Rn16
⯠PC â aa:16
⯠PC â @aa:8
⯠SPâ2 â SP
PC â @SP
PC â PC+d:8
2
4
2
4
2
4
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2
Condition Code
I HNZVC
â¯â¯â¯â¯â¯ 6
â¯â¯â¯â¯â¯ 2
â¯â¯â¯â¯â¯ 6
â¯â¯â¯â¯â¯ 6
â¯â¯â¯â¯â¯ 2
â¯â¯â¯â¯â¯ 6
â¯â¯â¯â¯â¯ 6
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 4
â¯â¯â¯â¯â¯â¯ 6
â¯â¯â¯â¯â¯â¯ 8
â¯â¯â¯â¯â¯â¯ 6
Rev. 8.00 Mar. 09, 2010 Page 537 of 658
REJ09B0042-0800
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