HD64F38024HV Datasheet, PDF (294/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 9 Timers
Bit 2—Compare Match Flag L (CMFL)
Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 2
CMFL
0
1
Description
Clearing condition:
After reading CMFL = 1, cleared by writing 0 to CMFL
Setting condition:
Set when the TCFL value matches the OCRFL value
(initial value)
Bit 1—Timer Overflow Interrupt Enable L (OVIEL)
Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows.
Bit 1
OVIEL
0
1
Description
TCFL overflow interrupt request is disabled
TCFL overflow interrupt request is enabled
(initial value)
Bit 0—Counter Clear L (CCLRL)
Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match.
Bit 0
CCLRL
0
1
Description
TCFL clearing by compare match is disabled
TCFL clearing by compare match is enabled
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 272 of 658
REJ09B0042-0800