HD64F38024HV Datasheet, PDF (190/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 6 ROM
Table 6.8
Item
Boot Mode Operation
Host Operation
Processing Contents
Bit rate
adjustment
Continuously transmits data H'00 at
specified bit rate.
Flash memory erase
Transmits data H'55 when data H'00
is received and no error occurs.
Transfer of
programming control
program
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data (low-order
byte following high-order byte)
Transfer of
programming control
program (repeated for
N times)
Transmits 1-byte of programming
control program
LSI Operation
Processing Contents
Branches to boot program at reset-start.
· Measures low-level period of receive data H'00.
· Calculates bit rate and sets it in BRR of SCI3.
· Transmits data H'00 to the host to indicate that the
adjustment has ended.
Checks flash memory data, erases all flash memory
blocks in case of written data existing, and transmits
data H'AA to host. (If erase could not be done,
transmits data H'FF to host and aborts operation.)
Echobacks the 2-byte received data to host.
Echobacks received data to host and also
transfers it to RAM.
Execution of
Programming
control program
Transmits 1-byte data H'AA to host.
Branches to programming control program
transferred to on-chip RAM and starts execution.
Table 6.9 Oscillating Frequencies (f_OSC) for which Automatic Adjustment of LSI Bit Rate
Is Possible
Product Group
F-ZTAT version of
H8/38024 Group and
F-ZTAT version of
H8/38024R Group
F-ZTAT version of
H8/38124 Group
Host Bit Rate
4,800 bps
2,400 bps
1,200 bps
19,200 bps
9,600 bps
4,800 bps
2,400 bps
1,200 bps
Oscillating Frequencies (f_OSC) Range of LSI
8 to 10 MHz
4 to 10 MHz
2 to 10 MHz
16 to 20 MHz
8 to 20 MHz
6 to 20 MHz
2 to 20 MHz
2 to 20 MHz
Rev. 8.00 Mar. 09, 2010 Page 168 of 658
REJ09B0042-0800