HD64F38024HV Datasheet, PDF (100/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 3 Exception Handling
Table 3.2 Interrupt Sources and Their Priorities
Interrupt Source Interrupt
Vector Number Vector Address Priority
RES
Reset
0
H'0000 to H'0001 High
Watchdog timer
IRQ0
LVDI*
IRQ1
IRQAEC
IRQ3
IRQ4
WKP0
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
Timer A
IRQ0
4
Low-voltage detect interrupt^*
IRQ1
5
IRQAEC
6
IRQ3
7
IRQ4
8
WKP0
9
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
Timer A overflow
11
H'0008 to H'0009
H'000A to H'000B
H'000C to H'000D
H'000E to H'000F
H'0010 to H'0011
H'0012 to H'0013
H'0016 to H'0017
Asynchronous
Asynchronous event
12
event counter
counter overflow
H'0018 to H'0019
Timer C
Timer C overflow or underflow 13
H'001A to H'001B
Timer FL
Timer FL compare match
14
Timer FL overflow
H'001C to H'001D
Timer FH
Timer FH compare match
15
Timer FH overflow
H'001E to H'001F
Timer G
Timer G input capture
16
Timer G overflow
H'0020 to H'0021
SCI3
SCI3 transmit end
18
SCI3 transmit data empty
SCI3 receive data full
SCI3 overrun error
SCI3 framing error
SCI3 parity error
H'0024 to H'0025
A/D
A/D conversion end
19
H'0026 to H'0027
(SLEEP instruction Direct transfer
executed)
20
H'0028 to H'0029 Low
Notes: Vector addresses H'0002 to H'0007, H'0014 to H'0015, and H'0022 to H'0023 are reserved
and cannot be used.
* The low-voltage detect interrupt triggered by the LVDI is only implemented on the
H8/38124 Group.
Rev. 8.00 Mar. 09, 2010 Page 78 of 658
REJ09B0042-0800