HD64F38024HV Datasheet, PDF (451/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Table 13.3 Output Levels
Data
M
Static
1/2 duty
1/3 duty
1/4 duty
Common output
Segment output
Common output
Segment output
Common output
Segment output
Common output
Segment output
0
0
V1
V1
V2, V3
V1
V3
V2
V3
V2
Section 13 LCD Controller/Driver
0
1
VSS
VSS
V2, V3
VSS
V2
V3
V2
V3
1
1
0
1
V1
VSS
VSS
V1
V1
VSS
VSS
V1
V1
VSS
VSS
V1
V1
VSS
VSS
V1
M: LCD alternation signal
13.3.3 Operation in Power-Down Modes
This LSI the LCD controller/driver can be operated even in the power-down modes. The
operating state of the LCD controller/driver in the power-down modes is summarized in table
13.4.
In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and
therefore, unless φw, φw/2, or φw/4 has been selected by bits CKS3 to CKS0, the clock will not be
supplied and display will halt. Since there is a possibility that a direct current will be applied to
the LCD panel in this case, it is essential to ensure that φw, φw/2, or φw/4 is selected. In active
(medium-speed) mode, the system clock is switched, and therefore CKS3 to CKS0 must be
modified to ensure that the frame frequency does not change.
Rev. 8.00 Mar. 09, 2010 Page 429 of 658
REJ09B0042-0800