HD64F38024HV Datasheet, PDF (42/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 1 Overview
Type
Clock
pins
Pin No.
FP-80A
Symbol TFP-80C FP-80B TLP-85V
OSC1 10
OSC2 9
12
F2
11
E3
X1
6
X2
7
8
D3
9
D2
System RES
12
control
TEST 11
14
F3
13
E2
Interrupt IRQ0
72
pins
IRQ1
76
IRQ3
5
IRQ4
3
IRQAEC 60
74
C5
78
B3
7
D1
5
B2
62
C10
Pad Pad Pad
No.^*1 No.^*2 No.^*3 I/O
Name and Functions
11 12 10 Input These pins connect to a
10 11 9
Output ^{crystal or ceramic}
oscillator, or can be used
to input an external clock.
See section 4, Clock
Pulse Generators, for a
typical connection
diagram.
6
7
6
Input These pins connect to a
7
8
7
Output ^{32.768-kHz or 38.4-kHz*5}
crystal oscillator.
See section 4, Clock
Pulse Generators, for a
typical connection
diagram.
13 14 12 Input Reset: When this pin is
driven low, the chip is
reset
12 13 11 Input Test pin: This pin is
reserved and cannot be
used. It should be
connected to VSS.
73 74 72 Input IRQ interrupt request 0,
77 78 76
1, 3, and 4: These are
5
6
5
input pins for edge-
3
4
3
sensitive external
interrupts, with a selection
of rising or falling edge
61 62 60 Input Asynchronous event
counter event signal:
This is an interrupt input
pin for enabling
asynchronous event
input.
On the H8/38124 Group,
this must be fixed at VCC
or GND because the
oscillator is selected by
the input level during
resets. Refer to section 4,
Clock Pulse Generators,
for information on the
selection method.
Rev. 8.00 Mar. 09, 2010 Page 20 of 658
REJ09B0042-0800