HD64F38024HV Datasheet, PDF (563/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Appendix A CPU Instruction Set
A.3 Number of Execution States
The tables here can be used to calculate the number of states required for instruction execution.
Table A.4 indicates the number of states required for each cycle (instruction fetch, read/write,
etc.), and table A.3 indicates the number of cycles of each type occurring in each instruction. The
total number of states required for execution of an instruction can be calculated from these two
tables as follows:
Execution states = I × S_I + J × S_J + K × S_K + L × S_L + M × S_M + N × S_N
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
S_I = 2, S_L = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1, L = M = N = 0
From table A.3:
S_I = S_J = S_K = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Table A.3 Number of Cycles in Each Instruction
Execution Status
(instruction cycle)
Access Location
On-Chip Memory
On-Chip Peripheral Module
Instruction fetch
SI
2
—
Branch address read
SJ
Stack operation
SK
Byte data access
SL
2 or 3^*
Word data access
SM
—
Internal operation
SN
1
Note: * Depends on which on-chip module is accessed. See section 2.9.1, Notes on Data Access
for details.
Rev. 8.00 Mar. 09, 2010 Page 541 of 658
REJ09B0042-0800