HD64F38024HV Datasheet, PDF (440/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 13 LCD Controller/Driver
Bit 4—Display Data Control (DISP)
Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless
of the LCD RAM contents.
Bit 4
DISP
0
1
Description
Blank data is displayed
LCD RAM data is display
(initial value)
Bits 3 to 0—Frame Frequency Select 3 to 0 (CKS3 to CKS0)
Bits 3 to 0 select the operating clock and the frame frequency. In subactive mode, watch mode,
and subsleep mode, the system clock (φ) is halted, and therefore display operations are not
performed if one of the clocks from φ/2 to φ/256 is selected. If LCD display is required in these
modes, φw, φw/2, or φw/4 must be selected as the operating clock.
Bit 3
CKS3
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Frame Frequency^*2
Operating Clock φ = 2 MHz
φ = 250 kHz^*1
0
*
0
0
φw
0
*
0
1
φw/2
0
*
1
*
φw/4
128 Hz^*3 (initial value)
64 Hz^*3
32 Hz^*3
1
0
0
0
φ/2
—
244 Hz
1
0
0
1
φ/4
977 Hz
122 Hz
1
0
1
0
φ/8
488 Hz
61 Hz
1
0
1
1
φ/16
244 Hz
30.5 Hz
1
1
0
0
φ/32
122 Hz
—
1
1
0
1
φ/64
61 Hz
—
1
1
1
0
φ/128
30.5 Hz
—
1
1
1
1
φ/256
—
—
*: Don’t care
Notes: 1. This is the frame frequency in active (medium-speed, φosc/16) mode when φ = 2 MHz.
2. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.
3. This is the frame frequency when φw = 32.768 kHz.
Rev. 8.00 Mar. 09, 2010 Page 418 of 658
REJ09B0042-0800