HD64F38024HV Datasheet, PDF (112/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 3 Exception Handling
Wakeup Edge Select Register (WEGR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn.
WEGR is initialized to H'00 by a reset.
Bit n—WKPn Edge Select (WKEGSn)
Bit n selects WKPn pin input sensing.
Bit n
WKEGSn
0
1
Description
WKPn pin falling edge detected
WKPn pin rising edge detected
(initial value)
(n = 7 to 0)
3.3.3 External Interrupts
There are 13 external interrupts: WKP7 to WKP0, IRQ4, IRQ3, IRQ1, IRQ0, and IRQAEC.
Interrupts WKP₇ to WKP₀
Interrupts WKP7 to WKP0 are requested by either rising or falling edge input to pins WKP₇ to
WKP₀. When these pins are designated as pins WKP₇ to WKP₀ in port mode register 5 and a
rising or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt.
Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in
IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When WKP7 to WKP0 interrupt exception handling is initiated, the I bit is set to 1 in CCR.
Vector number 9 is assigned to interrupts WKP7 to WKP0. All eight interrupt sources have the
same vector number, so the interrupt-handling routine must discriminate the interrupt source.
Rev. 8.00 Mar. 09, 2010 Page 90 of 658
REJ09B0042-0800