HD64F38024HV Datasheet, PDF (597/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

TCSRF—Timer Control/Status Register F
Appendix B Internal I/O Registers
H'B7
Timer F
Bit
Initial value
Read/Write
7
OVFH
0
R/(W)^*
6
CMFH
0
R/(W)^*
5
OVIEH
0
R/W
4
CCLRH
0
R/W
3
OVFL
0
R/(W)^*
2
CMFL
0
R/(W)^*
1
OVIEL
0
R/W
0
CCLRL
0
R/W
Counter Clear L
0 TCFL clearing by compare match is disabled
1 TCFL clearing by compare match is enabled
Timer Overflow Interrupt Enable L
0 TCFL overflow interrupt request is disabled
1 TCFL overflow interrupt request is enabled
Compare Match Flag L
0 Clearing condition:
After reading CMFL = 1, cleared by writing 0 to CMFL
1 Setting condition:
Set when the TCFL value matches the OCRFL value
Timer Overflow Flag L
0 Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
1 Setting condition:
Set when TCFL overflows from H'FF to H'00
Counter Clear H
0 16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
1 16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
Timer Overflow Interrupt Enable H
0 TCFH overflow interrupt request is disabled
1 TCFH overflow interrupt request is enabled
Compare Match Flag H
0 Clearing condition:
After reading CMFH = 1, cleared by writing 0 to CMFH
1 Setting condition:
Set when the TCFH value matches the OCRFH value
Timer Overflow Flag H
0 Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
1 Setting condition:
Set when TCFH overflows from H'FF to H'00
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
Rev. 8.00 Mar. 09, 2010 Page 575 of 658
REJ09B0042-0800