HD64F38024HV Datasheet, PDF (126/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 4 Clock Pulse Generators
IRQAEC
OSC1
OSC2
X1
X2
Internal reset signal (other than watchdog timer or low-voltage detect
circuit reset)
C
D
Q
Latch
System
clock
oscillator
φOSC
(fOSC)
System
clock
divider
(1/2)
On-chip _ROSC
oscillator
φOSC/2
System
clock
divider
φOSC/16
φOSC/32
φOSC/64
φOSC/128
System clock pulse generator
Subclock
φW
oscillator
(fW)
Subclock
divider
(1/2, 1/4, 1/8)
φW/2
φW/4
φW/8
Subclock pulse generator
φ
Prescaler S
(13 bits)
φ/2
to
φ/8192
φW
φSUB
Prescaler W
(5 bits)
φW/2
φW/4
φW/8
to
φW/128
Figure 4.2 Block Diagram of Clock Pulse Generators (H8/38124 Group)
4.1.2 System Clock and Subclock
The basic clock signals that drive the CPU and on-chip peripheral modules are φ and φ_SUB. Four
of the clock signals have names: φ is the system clock, φ_SUB is the subclock, φ_OSC is the oscillator
clock, and φ_W is the watch clock.
The clock signals available for use by peripheral modules are φ/2, φ/4, φ/8, φ/16, φ/32, φ/64,
φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φ_W, φ_W/2, φ_W/4, φ_W/8, φ_W/16, φ_W/32, φ_W/64,
and φ_W/128. The clock requirements differ from one module to another.
Rev. 8.00 Mar. 09, 2010 Page 104 of 658
REJ09B0042-0800