HD64F38024HV Datasheet, PDF (150/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 5 Power-Down Modes
Bit 2
MSON
0
1
Description
Operation in active (high-speed) mode
Operation in active (medium-speed) mode
(initial value)
Bits 1 and 0—Subactive Mode Clock Select (SA1, SA0)
These bits select the CPU clock rate (φ_W/2, φ_W/4, or φ_W/8) in subactive mode. SA1 and SA0
cannot be modified in subactive mode.
Bit 1
SA1
0
0
1
Bit 0
SA0
0
1
*
Description
φW/8
φW/4
φW/2
(initial value)
*: Don’t care
5.2 Sleep Mode
5.2.1 Transition to Sleep Mode
1. Transition to sleep (high-speed) mode
The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON and DTON
bits in SYSCR2 are cleared to 0. In sleep mode CPU operation is halted but the on-chip
peripheral functions. CPU register contents are retained.
2. Transition to sleep (medium-speed) mode
The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction
is executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in
SYSCR2 is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed)
mode, as in sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral
functions are operational. The clock frequency in sleep (medium-speed) mode is determined
by the MA1 and MA0 bits in SYSCR1. CPU register contents are retained.
Furthermore, it sometimes acts with half state early timing at the time of transition to sleep
(medium-speed) mode.
Rev. 8.00 Mar. 09, 2010 Page 128 of 658
REJ09B0042-0800