HD64F38024HV Datasheet, PDF (158/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 5 Power-Down Modes
5.5 Subsleep Mode
5.5.1 Transition to Subsleep Mode
The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D
converter and PWM is in active state. As long as a minimum required voltage is applied, the
contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules
are retained. I/O ports keep the same states as before the transition.
5.5.2 Clearing Subsleep Mode
Subsleep mode is cleared by an interrupt (timer A, timer C, timer F, timer G, asynchronous event
counter, SCI3, IRQAEC, IRQ₄, IRQ₃, IRQ₁, IRQ₀, WKP₇ to WKP₀) or by a low input at the RES
pin.
• Clearing by interrupt
When an interrupt is requested, subsleep mode is cleared and interrupt exception handling
starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
To synchronize the interrupt request signal with the system clock, up to 2/φ_SUB(s) delay may
occur after the interrupt request signal occurrence, before the interrupt exception handling
start.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see Clearing by RES pin in section
5.3.2, Clearing Standby Mode.
Rev. 8.00 Mar. 09, 2010 Page 136 of 658
REJ09B0042-0800