HD64F38024HV Datasheet, PDF (371/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 10 Serial Communication Interface
Bit 2—Transmit End (TEND)
Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent.
Bit 2 is a read-only bit and cannot be modified.
Bit 2
TEND
0
1
Description
Transmission in progress
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
Transmission ended
(initial value)
Setting conditions:
When bit TE in SCR3 is cleared to 0
When bit TDRE is set to 1 when the last bit of a transmit character is sent
Bit 1—Reserved (MPBR)
It’s a reserved read-only bit.
Bit 0—Reserved (MPBT)
The write value should always be 0.
Rev. 8.00 Mar. 09, 2010 Page 349 of 658
REJ09B0042-0800