HD64F38024HV Datasheet, PDF (109/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 3 Exception Handling
Bit 6—A/D Converter Interrupt Request Flag (IRRAD)
Bit 6
IRRAD
0
1
Description
Clearing condition:
When IRRAD = 1, it is cleared by writing 0
(initial value)
Setting condition:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
Bit 5—Reserved
Bit 5 is reserved: it can only be written with 0.
Bit 4—Timer G Interrupt Request Flag (IRRTG)
Bit 4
IRRTG
0
1
Description
Clearing condition:
When IRRTG = 1, it is cleared by writing 0
(initial value)
Setting condition:
When the TMIG pin is designated for TMIG input and the designated signal edge is
input, and when TCG overflows while OVIE is set to 1 in TMG
Bit 3—Timer FH Interrupt Request Flag (IRRTFH)
Bit 3
IRRTFH
0
1
Description
Clearing condition:
When IRRTFH = 1, it is cleared by writing 0
(initial value)
Setting condition:
When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH)
and OCRF (OCRFL, OCRFH) match in 16-bit timer mode
Rev. 8.00 Mar. 09, 2010 Page 87 of 658
REJ09B0042-0800