HD64F38024HV Datasheet, PDF (458/684 Pages) Renesas Technology Corp – Hardware Manual Renesas 8-Bit Single-Chip Microcomputer H8 Family/H8/300L Super Low Power Series

Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only)
Table 14.3 shows the relationship between LVDCR settings and function selections. Refer to table
14.3 when making settings to LVDCR.
Table 14.3 LVDCR Settings and Function Selections
LVDE
LVDCR Setting Value
Power-on
LVDSEL LVDRE LVDDE LVDUE Reset
Low-Voltage
Detection
Reset
Low-Voltage
Detection
Voltage Drop
Interrupt
Low-Voltage
Detection
Voltage Rise
Interrupt
0
*
*
*
*
—
—
—
1
1
1
0
0
—
—
1
0
0
1
0
—
—
1
0
0
1
1
—
1
0
1
1
1
Note: Setting values marked with an asterisk (*) are invalid.
14.2.2 Low-Voltage Detection Status Register (LVDSR)
Bit
7
6
5
4
3
2
OVF
—
—
— VREFSEL —
Initial value
0^*
0
0
0
0
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
Note: * These bits initialized by resets trigged by LVDR.
1
LVDDF
0^*
R/W
0
LVDUF
0^*
R/W
LVDSR is an 8-bit read/write register. It is used to control external input selection, indicates when
the reference voltage is stable, and indicates if the power supply voltage goes below or above a
specified range.
Bit 7—LVD Reference Voltage Stabilized Flag (OVF)
This bit indicates when the low-voltage detection counter (LVDCNT) overflows.
Bit 7
OVF
0
1
Description
[Clearing condition]
When 0 is written after reading 1
[Setting condition]
When the low-voltage detection counter (LVDCNT) overflows
(initial value)
Rev. 8.00 Mar. 09, 2010 Page 436 of 658
REJ09B0042-0800